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NEWS & EVENTS

In the News


2013 Articles
 
None   Analysis of HLS Results Made Easier
7/10/2013
Randysan
SemiWiki.com
     
None   Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemC
dvcon.org
     
None   SystemC HLS Optimizes Power
6/18/2013
Bryon Moyer
eejournal.com
     
None   Reducing Power by Raising the Level of Abstraction
5/30/2013
soccentral.com
     
None   Forte CEO on Design and Verification Complexity
5/10/2013
Daniel Nenni
SemiWiki.com
     
None   Reduce Errors in Multi-threaded Designs Using an Interface Generator
4/28/2013
Randysan
SemiWiki.com
     
None   Forte Rises
3/29/2013
Randysan
SemiWiki.com

2012 Articles
 
Gabe on EDA   A return to EDA and a Renewed Commitment to High-Level Synthesis
8/2012
David Pursley
Forte Design Systems
     
EE Times   Control dominated design
7/14/2012
Mike Meredith
Forte Design Systems
     
EE Times   2012 will be the year of power, again
4/25/2012
Brett Cline
Forte Design Systems
     
EDACafe   What would Joe do? Forte: Anchor Tenant in the ESL Mall
4/25/2012
Peggy Aycinena, Editor of EDA Confidential
EDACafe
 
     
EDN   Sage words of advice from Forte Design Systems founder John Sanguinetti
4/19/2012
Brian Bailey
EDN
     

2011 Articles
 
EE Times   The future is High-Level Synthesis
2/4/2011
Sean Dart
Forte Design Systems
     

2010 Articles
 
EDA DesignLine   High-level synthesis, verification and language
2/22/2010
John Sanguinetti
Forte Design Systems
     
SCDsource   Is HLS finally converging on a standard language?
2/16/2010
Brett Cline
Forte Design Systems
     
Chip Estimate   The next IC design methodology transition is long overdue
2/9/2010
Michael Meredith, Open SystemC Initiative, Forte Design Systems
Steve Svoboda, Open SystemC Initiative, Cadence
     

2009 Articles
 
IC Design and Verification Journal   Living With Ambiguity: The Other HLS
10/27/2009
Bryon Moyer
IC Design and Verification Journal
     
SCDsource   Forte acquires Arithmatica
9/28/2009
Bill Murray
SCDsource
     
EDN   Forte's acquisition of Arithmatica could open a new style for datapath design
9/28/2009
EDN Executive Editor Ron Wilson
Practical Chip Design on EDN
     
SCDsource   Forte boosts Cynthesizer's automation capabilities
8/27/2009
Bill Murray
SCDsource
     
Chip Design   Experts at the Table: Evolving Standards
8/27/2009
Ed Sperling
Chip Design
 
     
Automotive DesignLine   Viewpoint: Tesla, design and the art of innovation
7/24/2009
John Sanguinetti, CTO, Forte Design Systems
Automotive DesignLine
 
     
Chip Design   Experts at the Table: ESL and Low Power
7/16/2009
Ed Sperling
Chip Design
 
     
EDA DesignLine   The ESL battle for hearts and minds
7/1/2009
Peggy Aycinena
EDA DesignLine
 
     
EDACafe   C-Synthesis is for Everyone
5/2009
Sean Dart, CEO, Forte Design Systems
EDACafe View from The Top Executive Audio Interviews
 
     
EE Times   Viewpoint: More to IP reuse than software tweaks
2/25/2009
Mike Meredith, VP Technical Marketing, Forte Design Systems
EE Times
 
     
EDACafe   Bee in the Bonnet, Bug on the Loose
2/23/2009
Peggy Aycinena
EDACafe
 
     
EDA DesignLine   Behavioral Design Drives Low-Power Silicon
2/16/2009
Brett Cline, VP Marketing & Sales, Forte Design Systems
Mike Meredith, VP Technical Marketing, Forte Design Systems
EDA DesignLine
 
     
Electronic Design   Algorithmic Design Starts At The Top
2/12/2009
Dave Maliniak
Electronic Design
 
     
EDA DesignLine   Abstraction and Control-Dominated Hardware Designs
2/6/2009
John Sanguinetti, CTO, Forte Design Systems
EDA DesignLine
 
     
Chip Design   Not Everyone Feels the Pinch
1/18/2009
Ed Sperling
Chip Design
 
     

2008 Articles

  ESL Synthesis Innovation: The Importance of Choosing the Right Technology
Mike Meredith, VP Marketing, Forte Design Systems
9/17/2008
DACeZine
 
     
  Best and Worst Tools of DAC 2008
9/18/2008
DeepChip
 
     
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Archives
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2003

 

Must Reads
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"A look inside behavioral synthesis"
 




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