HIGH-LEVEL DESIGN  | PRODUCTS

Cynthesizer Closes the ESL-to-Silicon Gap

Cynthesizer is the first high-level design solution that closes the gap between ESL design and RTL-to-GDSII flows. It provides a complete design environment that includes behavioral synthesis and verification as well as FPGA prototyping and design management. Cynthesizer generates production-quality RTL using a high-level SystemC-TLM design description as input. Cynthesizer makes high-level design practical by accelerating architecture exploration and providing the fastest path to silicon-proven RTL. Cynthesizer provides an open and customizable environment based on standard languages and APIs. It integrates a complete tool chain that includes leading EDA products, accelerating the adoption of ESL design and reducing the cost of deployment.

Cynthesizer has been proven in production to provide numerous benefits:

• Fast system-architecture exploration with TLM Synthesis

• 50X-200X simulation speed-up over RTL with TLM verification

• Optimized RTL generation for ASICs, SoCs, and FPGAs

• 2X-4X faster implementation from spec to netlist over RTL

• Reduced silicon area and power consumption

• Fewer design iterations and faster design closure to back-end

• Rapid design derivatives with behavioral and interface IP
   

Cynthesizer completes the design flow from ESL to GDSII

Cynthesizer is the first high-level, block-based design and verification solution that links ESL design with RTL-to-GDSII flows through its unique TLM platform and rapid behavioral synthesis and verification methodology.

By accelerating the hardware design and verification process, Cynthesizer enables designers to explore multiple implementation solutions to optimize the SoC architecture earlier in the design project.

By generating high-quality RTL, Cynthesizer reduces errors early in the design flow, minimizes iterations with the back-end, and accelerates design closure.

By providing superior quality-of-results and the ability to trade-off area, performance, and power, Cynthesizer enables designers to optimize a design for the specific target application and shorten project turnaround time.

Cynthesizer incorporates a number of key capabilities that accelerate the overall design process:

System Design with Interface IP

Cynthesizer's interface IP provides the ability to implement alternative SoC design configurations through streaming interfaces, standard memories, FIFOs, and hierarchical channels. Its ability to instantly switch between transaction-level and pin-level interfaces makes it possible to explore a wide variety of communication protocols to achieve optimal application performance.

TLM Synthesis and Verification

Cynthesizer is the first high-level design solution that implements a top-down verification flow letting you synthesize and verify the same source. By using the same transaction-level models (TLM) for verification and implementation, Cynthesizer reduces errors, accelerates system architecture exploration, and streamlines the hardware and software design process.

Hardware Block Implementation

Cynthesizer provides a fully integrated environment for hierarchical block-based behavioral synthesis, design management, and verification using the same testbench throughout the design flow. Cynthesizer generates high-quality RTL optimized for leading logic synthesis and FPGA tools. Its quality has been proven in dozens of production SoCs.

Design Closure with the Back-end

Cynthesizer provides visibility into the quality-of-results much earlier in the design project. It provides the fastest path to production implementation through a rapid synthesis/verification/debug process, higher-quality RTL code, and reduced iterations with the back-end. Cynthesizer closes the ESL-to-silicon gap by implementing a fully integrated flow that incorporates existing RTL-to-GDSII tools.
 

Cynthesizer provides a state-of-the-art design environment

Cynthesizer includes a verification environment that uses a SystemC-TLM design specification as its input. It generates high-quality RTL that is directly used by leading synthesis and RTL verification tools.

Cynthesizer reads ASIC or FPGA libraries along with directives to produce multiple RTL implementations optimized for area, performance, and power to achieve the best fit for the target application.

Cynthesizer automates most of the tedious RTL design tasks including scheduling, allocation, and FSM creation. With its intelligent sharing and power optimization, Cynthesizer has been proven to create superior hardware results.

Cynthesizer creates high-quality RTL optimized for logic or FPGA synthesis, which manages risk earlier in the project and accelerates the design process.

Cynthesizer provides a complete environment for high-level debugging, synthesis, and analysis using leading third-party tools. With its extensive set of reports for source-to-RTL analysis, design analysis, and quality-of-results analysis, Cynthesizer supports rapid trade-off of area, power, and timing to achieve design closure.
 

Cynthesizer implements a sophisticated dependency-management capability to simplify the design and verification of complex hierarchical sub-systems with configurable interfaces. By integrating more third-party EDA tools in a managed flow than any other high-level design tool, and implementing a powerful process automation capability, Cynthesizer streamlines the design process. Cynthesizer reduces design iterations and accelerates progress to production silicon.
 

PDF Format:
Cynthesizer Brochure
 

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TLM Synthesis