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 IP
reuse has been a key strategy for dealing with increasing SoC complexity.
However, the value of IP reuse varies depending upon the target
application, design objectives, and product differentiation factors.
In the few cases where it can be directly reused, hard IP retains a high
time-to-market value. However, it is inflexible and cannot be easily
retargeted to new process technologies or changing functional requirements.
Soft IP (typically RTL code) offers more flexibility and is process
independent. However, it offers only marginal improvement in maintaining
cost/performance targets across uses because it is usually designed to take
advantage of a specific application and process.
For example, when moving to a smaller process technology there is
limited flexibility to reuse soft RTL-based IP. When faced with the
following challenge, one design team using Cynthesizer found they could not
completely realize expected performance gains by re-targeting soft
RTL-based IP.
Consider that team’s predicament:
A DCT block had been created using a conventional RTL design methodology
for a video encoding device running at 100MHz on a 180nm silicon process.
The next generation of the design required a 4x data rate increase. By
re-targeting to a 130nm technology library, the design team quickly found a
solution that would increase the clock speed by 2x, doubling the data rate.
However, that was still only half the speed of the design goal.
How to proceed? Was it time to create a new DCT block from scratch?
Introducing Cynthesizer for this design saved the team weeks of engineering
time.
A C++ behavioral model of the block existed from the original project.
The design team used this model as the basis of their behavioral design
using Cynthesizer. This produced comparable area and performance to the
existing 180nm implementation. Next, they attempted to increase the data
rate by 4x starting with the original behavioral design.
| Process / Clock Frequency |
RTL Reuse |
Cynthesizer Reuse |
| 180 nm / 100 MHz |
Base |
Base |
| 130 nm / 100 MHz |
YES |
YES |
| 130 nm / 200 MHz |
YES |
YES |
| 130 nm / 400 MHz |
NO |
YES |
| 130 nm / 200 MHz with ½ latency |
NO |
YES |
They switched the target technology to 130nm and retargeted the design to
run at 400MHz by providing Cynthesizer with the appropriate library and
setting the clock speed directive. In just a day, Cynthesizer was able to
create RTL that met the 4x data rate goal using these settings. In fact,
the design team discovered they could obtain even better results by running
the design at 200MHz and cutting the latency (number of clock cycles per
data element) in half. The best implementation, the team leader noted,
would not have even been considered if they had written RTL by hand.
For situations like this and many others, behavioral IP provides greater
flexibility than existing soft, RTL-based IP. A number of companies are now
following this Cynthesizer team and are developing their own repositories
of behavioral IP and creating reuse opportunities never available before.
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