|
Many design teams are using high-level design on new projects to better
manage design complexity and reduce the design cycle. High-level models
have been used extensively to describe and evaluate complex systems, but
until recently there has not been an effective and direct way to use those
models to obtain an optimized hardware implementation.
There are numerous ways that any function can be implemented in
hardware. RTL design requires decisions to be made early in the process,
which makes it difficult to find an optimum solution for the specific
application and process technology. Often, better implementations can be
found, but these may require a complete rewrite of the RTL. Tight project
deadlines and schedules seldom allow for such exploration, which limits
design choices and makes it harder to achieve design closure on time.
By
moving to a high-level design process, a larger assortment of hardware
implementation options can be reached from a single high-level description.
The designer controls automated scheduling of operations and the mapping of
the function into hardware constructs without changing the behavioral
source code. As a result, designers can chose the option that best fits
their SoC design objectives.
The behavioral source code is written in high-level SystemC, a C++ class
library that adds hardware constructs to the C++ language to bridge the gap
between software and hardware implementation of a function. This source
code does not contain timing information, nor does it imply a certain
datapath structure. Instead, constraints defined by the designer direct
Cynthesizer to create a faster, smaller, or lower-power RTL implementation
to achieve the optimal trade-off among the three.
One behavioral description allows the designer to explore the design
space by creating many different RTL implementations. Even design
characteristics as fundamental as the clock speed (100 MHz vs. 200 MHz),
target technology (ASIC vs. FPGA), and technology feature size (130nm vs.
90nm) can be effectively considered with only a single behavioral
description.
By using a behavioral design that is independent of the RTL
micro-architecture, the design blocks can be easily reused for different
applications. For this reason, a number of companies are developing their
own repositories of behavioral IP to improve reuse opportunities for future
projects.
Designing at a higher level of abstraction delivers the following
benefits:
- Fewer lines of
code boost productivity and minimize errors
- Broader set
of implementation alternatives reduce design cost and risk
- Faster
turnaround time to hardware with higher coverage
Find out more about high-level design and behavioral synthesis with
Cynthesizer
|
